CUDA 13.4 Delivers Windows on Arm, Rubin Preview, and Smarter Shared GPU Control

Windows on Arm Becomes First-Class CUDA Target

CUDA Toolkit 13.4 landed on September 9, 2026 with a feature set that redraws where and how AI developers can run GPU workloads: Windows on Arm support, a preview toolchain for the NVIDIA Rubin architecture, and a new control layer for shared GPUs.

NVIDIA’s developer blog published the full technical breakdown of the release on the same day.

The update matters beyond the usual toolkit cadence because it reaches into three pressure points at once: edge and laptop development on Arm silicon, multi-tenant GPU serving in containerized fleets, and the next generation of AI silicon that will power agentic workloads.

Inside the 13.4 Toolchain: Shared GPU Control, Fabric Transport, and Python Upgrades

The release splits into two complementary tracks: infrastructure control for shared GPU fleets and developer-facing abstraction for high-performance algorithms.

MPS V3: Container-Native GPU Partitioning

The most operationally significant change, as detailed in NVIDIA’s technical breakdown, is Multi-Process Service V3.

MPS V3 replaces an older control plane with a scriptable command-line interface, named server instances, and namespaces for concurrent workloads.

It adds TOML configuration, streaming multiprocessor partition controls, and cgroup-integrated memory limits for GPU allocation.

That means orchestration layers can define compute performance, memory boundaries, and execution priority programmatically instead of relying on static process isolation.

For AI serving environments running multiple inference models on one GPU, the result is tighter resource isolation and better hardware utilization in containerized deployments.

Compute Fabric Transport Rethinks NVLink Data Movement

CUDA Compute Fabric Transport introduces a transport-centric API for communication-library developers who need fine-grained control over NVLink fabric at scale.

Instead of mapping every remote GPU allocation into virtual address space, software targets named logical endpoints with an endpoint ID and offset.

It supports asynchronous put, get, and reduction operations issued directly from the GPU, along with unicast and multicast communication patterns.

Completion and error status signals allow applications to detect, retry, or reroute failed fabric transfers.

The API is available only through the CUDA Driver API and is aimed at communication-library builders, not most application developers.

Higher-level libraries such as NCCL and NVSHMEM remain the recommended path for standard multi-GPU workloads.

CUDA Python and CCCL Make GPU Algorithms Easier to Deploy

The Python side moves forward with cuda.core 1.1.0 and cuda.compute 1.1.

New texture and surface programming APIs expose hardware-laid-out GPU allocations through OpaqueArray, MipmappedArray, TextureObject, and SurfaceObject.

Managed memory now includes a property-based interface for read-mostly data, preferred placement, and processor access, with a Host type that can represent a specific NUMA node.

IDE type stubs, graph-definition capture, and path-like inputs reduce friction for Python-first CUDA work and coding agents.

On the algorithm side, cuda.compute 1.1 enables ahead-of-time compilation for multiple GPU architectures, including build systems that do not have a GPU installed.

ProxyArray and ProxyValue describe argument types without allocating device memory, while serialized artifacts can be deployed and deserialized on target systems.

CCCL 3.4 introduces a warp-specialized cub::DeviceScan for Blackwell GPUs.

The implementation uses the Tensor Memory Accelerator to overlap memory movement with computation and reduce synchronization overhead.

Vendor-reported benchmark data shows cub::DeviceScan::Sum reaching up to 92 percent memory-bandwidth utilization on a Blackwell part, compared with roughly 50 percent in a previous implementation.

That figure is a vendor-reported result from a specific tested data type set, not an independent third-party benchmark.

CCCL 3.4 also completes single-call overloads across CUB device-wide algorithms and adds batched warp reductions plus C++ Standard Library parallel algorithms under the cuda::execution::gpu policy.

The single-call environment-based API obtains temporary storage from a supplied memory resource, eliminating the classic two-step size query and allocation sequence for many workloads.

Locality, Residency, and Installer Changes

CUDA 13.4 exposes programmatic access to locality domains, portions of a GPU that contain streaming multiprocessors and device memory.

An application can allocate memory in a locality domain and create a green context with SM resources in the same domain, placing computation close to the memory it accesses.

Unified memory residency queries through cudaMemGetLocationInfo give performance-sensitive libraries direct visibility into where managed or system-allocated data resides at a given time.

That reduces the guesswork that often produces unnecessary page migrations and remote memory access.

The toolkit also decouples SDK installers from the NVIDIA driver bundle, requiring users to install nvidia-open or cuda-toolkit packages separately through a package manager.

Rubin Preview and the Agentic AI Compute Roadmap

Support for Windows on Arm is not a marginal portability checkbox.

It puts CUDA application development on the same Arm-based Windows hardware that is becoming common in edge AI, developer workstations, and N1X laptop-class systems.

Core math libraries now support Windows on Arm for the N1X Laptop ecosystem, which points to a broader push beyond Linux-only Arm development.

The Rubin preview is the more consequential signal for AI infrastructure planners.

Compute capability 107 is available as functional support, which lets developers start porting workloads before general availability arrives in a later toolkit release.

Because Rubin is positioned as the next-generation architecture for agentic AI, teams that begin validating memory patterns, kernel behavior, and scheduling assumptions now can compress their adoption window later.

MPS V3 and Compute Fabric Transport are aimed at exactly the kind of multi-tenant, high-density GPU fleets that agentic AI serving requires.

Precise GPU partitioning and programmatic fabric transfers reduce wasted capacity and give orchestration layers better control over latency-sensitive inference and large-scale data movement.

Together, these changes make CUDA 13.4 less of a passive toolchain update and more of an infrastructure-enablement layer for the next hardware and workload cycle.

Organizations running large AI fleets should treat the release as an early readiness signal rather than a routine patch cycle.

The CUDA Fleet Calculus Has Changed

CUDA 13.4 moves the developer stack from per-workstation compilation toward container-native GPU scheduling and next-generation silicon readiness in a single release.

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