Key Takeaways
- The Olympus core is designed to maximize single-thread performance for irregular, branch-heavy agent workloads, leveraging advanced branch prediction and deep out-of-order execution.
- NVIDIA Spatial Multithreading (SMT) partitions core resources to reduce noise from sibling threads, delivering more predictable latency under high concurrency.
- In benchmark tests, the Vera CPU achieved up to 1.8x higher performance on agentic tasks compared to AMD EPYC, with 2.6x faster graph traversal over AMD Turin.
NVIDIA Vera CPU Arrives: A New Era for Agentic AI Computing
NVIDIA today pulled back the curtain on its Vera CPU, a processor built from the ground up to accelerate the irregular, branch-heavy software paths that define modern agentic AI. Powered by the new Olympus core, the Vera CPU targets the exact pain point that legacy x86 architectures struggle with: sustaining high single-thread performance under full socket load. As agents execute code, invoke tools, and traverse complex data structures, the CPU’s ability to maintain per-thread throughput directly shapes AI factory responsiveness and overall throughput.
This processor is not just another server chip. It represents a fundamental rethinking of CPU design for the era of autonomous AI agents. The Vera CPU integrates 88 Olympus cores with 176 hardware threads, a unified 164 MB L3 cache, and up to 1.2 TB/s of memory bandwidth via SOCAMM2 LPDDR5X modules. The engineering team at NVIDIA has openly acknowledged that agentic workloads require a different focus: maximizing instructions per cycle through deeper out-of-order execution and advanced branch prediction rather than relying on clock frequency alone.
Table of Contents
Olympus Core: Engineered for Agentic Workloads
The Olympus core is a custom design focused on maximizing IPC for highly concurrent AI infrastructure workloads. It features a 10-wide decode engine, a neural branch predictor that achieves higher accuracy on biased branch patterns, and a large reorder buffer that keeps more instructions in flight. The combination allows the core to maintain strong performance even when executing pointer-heavy, latency-sensitive code typical of agent runtimes and graph analytics.
The mid core integrates a wide rename and allocation engine with dependency-breaking capabilities such as memory renaming and value prediction. These features reduce stalls from serialized memory operations and long dependency chains, enabling the execution engine to remain productive. NVIDIA’s engineers have stressed that this is critical for the bursty, event-driven nature of agent workflows, where each step depends on the outcome of previous operations.
On the cache side, Olympus includes a graph prefetcher designed to handle irregular memory access patterns. Traditional prefetchers struggle with pointer chasing and sparse data structures, but the graph prefetcher anticipates these accesses, reducing effective memory latency. The core also supports deep memory-level parallelism, allowing multiple memory requests to be in flight simultaneously.
Spatial Multithreading: Predictable Performance Under Load
Multithreading is critical for agentic AI, where each sandbox may require multiple threads for I/O, logging, and tool orchestration alongside the primary execution path. Traditional simultaneous multithreading (SMT) shares resources opportunistically, which can cause performance variability and noisy-neighbor effects. NVIDIA’s Spatial Multithreading takes a different approach by partitioning core resources more effectively across two hardware threads.
In Spatial Multithreading mode, the wide Olympus core can allocate resources like the reorder buffer, execution ports, and cache capacity such that one thread’s activity does not degrade the other’s performance. This enables predictably high single-thread throughput even when both threads are active. When maximum per-thread performance is needed, the sibling thread can be used for management tasks without slowing the primary thread. The result is more consistent latency and higher utilization across the 176 threads of a dual-socket configuration.
High-Bandwidth Fabric and Memory to Feed the Cores
The Vera CPU pairs the Olympus cores with the NVIDIA Scalable Coherency Fabric (SCF), a monolithic on-die interconnect that provides up to 3.4 TB/s of bandwidth. The SCF integrates a 164 MB unified L3 cache accessible by all cores, avoiding the die-hop latency penalties common in chiplet-based designs. This is vital for agents that frequently share state and traverse shared data structures across multiple cores.
Memory bandwidth is delivered through SOCAMM2 LPDDR5X modules, which offer up to 1.2 TB/s aggregate bandwidth and 14 GB/s per core. This is significantly higher than traditional DDR5 or MRDIMM designs, and the LPDDR5X operates at lower power, contributing to overall platform efficiency. The use of modular, field-replaceable modules ensures datacenter serviceability while maintaining the short electrical paths necessary for high-speed signaling.
The memory subsystem also supports RAS features critical for AI factory reliability, including error correction and predictive failure analysis. With large working sets and irregular access patterns in agent workloads, the combination of high bandwidth and low latency is essential to keep execution units fed.
Benchmark Dominance and Market Implications
Early benchmarks indicate that the Vera CPU’s architecture provides substantial performance advantages over existing x86 competitors. According to internal NVIDIA measurements, the Vera CPU delivers up to 1.8x higher performance on agentic workloads compared to AMD’s EPYC processors. These gains extend to specific use cases: graph traversal performance is 2.6x faster than AMD’s Turin-generation chips, according to GamesBeat. Similarly, coding workflows see a 1.5x improvement over Intel’s Granite Rapids and AMD’s Zen 5-based server chips, with compilation and static analysis tasks completing significantly faster.
The real-world impact is already being measured. A recent dropreference analysis noted that the Vera CPU is approximately 10-11% ahead of the current EPYC 9575F on latency-sensitive agent-based tasks. While AMD’s EPYC Turin remains competitive in some multi-threaded throughput benchmarks, the Vera CPU’s lead in single-thread performance under load positions it uniquely for the agentic AI market. Intel’s Granite Rapids, meanwhile, faces challenges in scaling single-thread performance across its monolithic cores, though it still offers competitive features.
For the data center industry, this shift means that software teams can expect more predictable performance and simpler tuning for agentic AI workloads. The single-NUMA dual-socket design reduces topology complexity, a departure from the multi-die NUMA domains common in x86. As AI factories scale to thousands of nodes, the Vera CPU’s consistency and per-thread performance could become a decisive factor in deployment decisions.
Vera CPU Sets the Stage for Next-Gen AI Factories
The NVIDIA Vera CPU represents a turning point in processor design for AI infrastructure. By prioritizing single-thread performance through custom architecture rather than brute-force frequency scaling, NVIDIA has addressed the specific computational requirements of agentic AI and reinforcement learning. The integration of Spatial Multithreading, a coherent fabric, and high-bandwidth memory creates a balanced platform that reduces variability and improves throughput across concurrent agent tasks.
As the AI industry moves toward autonomous agents operating at unprecedented scale, the Vera CPU’s architecture, detailed in NVIDIA’s technical blog, offers a preview of how CPU and GPU co-design will evolve. The combination of the Olympus core and the Rubin GPU family, connected via NVLink-C2C, enables a unified platform where CPU and GPU work in concert to accelerate the entire AI lifecycle. Enterprises and cloud providers evaluating next-generation infrastructure should consider the implications of moving beyond traditional x86 designs to maximize agentic AI performance.
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Frequently Asked Questions
What makes the NVIDIA Vera CPU different from traditional server CPUs for AI workloads?
The Vera CPU is custom-built for agentic AI, focusing on maximizing instructions per cycle (IPC) through a 10-wide decode engine, neural branch predictor, and large reorder buffer, rather than relying on clock frequency. It excels at irregular, branch-heavy code paths typical of AI agents, whereas legacy x86 architectures struggle to sustain high single-thread performance under full socket load.
How does Spatial Multithreading improve performance over traditional SMT?
NVIDIA’s Spatial Multithreading partitions core resources like the reorder buffer and cache more effectively across two hardware threads, ensuring one thread’s activity does not degrade the other’s performance. This provides predictably high single-thread throughput even when both threads are active, reducing noisy-neighbor effects common in traditional simultaneous multithreading (SMT).
What memory technology does the Vera CPU use and what bandwidth does it provide?
The Vera CPU uses SOCAMM2 LPDDR5X modules, delivering up to 1.2 TB/s aggregate bandwidth and 14 GB/s per core. This is significantly higher than traditional DDR5 or MRDIMM designs, and operates at lower power. The memory subsystem also includes RAS features like error correction and predictive failure analysis for AI factory reliability.
How does the Vera CPU compare to AMD EPYC and Intel Granite Rapids in benchmarks?
According to NVIDIA, the Vera CPU delivers up to 1.8x higher performance on agentic workloads versus AMD EPYC, with graph traversal up to 2.6x faster and coding workflows up to 1.5x better than Intel Granite Rapids and AMD Zen 5. Independent analysis shows it is about 10-11% ahead of the EPYC 9575F on latency-sensitive agent tasks.
What is the purpose of the graph prefetcher in the Olympus core?
The graph prefetcher handles irregular memory access patterns, such as pointer chasing and sparse data structures, which traditional prefetchers struggle with. By anticipating these accesses, it reduces effective memory latency and improves performance for agent workflows that traverse complex data structures.
What is the significance of the single-NUMA dual-socket design in the Vera CPU?
The single-NUMA dual-socket design reduces topology complexity compared to multi-die NUMA domains common in x86 processors. This simplifies software tuning and provides more predictable performance, which is critical for scaling AI factories to thousands of nodes.
How does the Vera CPU integrate with NVIDIA’s Rubin GPU family?
The Vera CPU connects to the Rubin GPU family via NVLink-C2C, enabling a unified platform where CPU and GPU work in concert to accelerate the entire AI lifecycle. This co-design approach allows efficient handling of agentic AI tasks that require both high single-thread CPU performance and massive GPU parallelism.
